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950 mhz to 1575 mhz quadrature modulator with integrated fractional-n pll and vco adrf6750 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2010 analog devices, inc. all rights reserved. features i/q modulator with integrated fractional-n pll and vco gain control span: 47 db in 1 db steps output frequency range: 950 mhz to 1575 mhz output 1 db compression: 8.5 dbm output ip3: 23 dbm noise floor: ?162 dbm/hz baseband modulation bandwidth: 250 mhz (1 db) output frequency resolution: 1 hz functions with external vco for extended frequency range spi and i 2 c-compatible serial interfaces power supply: 5 v/310 ma general description the adrf6750 is a highly integrated quadrature modulator, frequency synthesizer, and programmable attenuator. the device covers an operating frequency range from 950 mhz to 1575 mhz for use in satellite, cellular and broadband communications. the adrf6750 modulator includes a high modulus fractional-n frequency synthesizer with integrated vco, providing better than 1 hz frequency resolution, and a 47 db digitally controlled output attenuator with 1 db steps. control of all the on-chip registers is through a user-selected spi interface or i 2 c interface. the device operates from a single power supply ranging from 4.75 v to 5.25 v. functional block diagram qbbp qbbn rset testlo testlo sdi/sda clk/scl sdo cs txdis agnd dgnd 2 doubler 5-bit divider reference charge pump current setting refin refin 2 phase frequency detector + ? output stage vco core 0/90 regout v cc1 v cc2 v cc3 v cc4 adrf6750 vreg1 vreg2 vreg3 vreg4 vreg5 vreg6 lomonp lomonn rfout 47db gain control range n-counter integer register fractional register modulus 2 25 third-order fractional interpolator rfcp4 rfcp3 rfcp2 rfcp1 cp lf3 lf2 ldet ibbp ibbn ccomp1 ccomp2 ccomp3 vtune 3.3v regulator spi/ i 2 c interface 08201-001 figure 1.
adrf6750 rev. a | page 2 of 40 table of contents features .............................................................................................. 1 ? general description ......................................................................... 1 ? functional block diagram .............................................................. 1 ? revision history ............................................................................... 2 ? specifications ..................................................................................... 3 ? timing characteristics ................................................................ 5 ? absolute maximum ratings ............................................................ 7 ? esd caution .................................................................................. 7 ? pin configuration and function descriptions ............................. 8 ? typical performance characteristics ........................................... 10 ? theory of operation ...................................................................... 18 ? overview ...................................................................................... 18 ? pll synthesizer and vco ......................................................... 18 ? quadrature modulator .............................................................. 20 ? attenuator .................................................................................... 21 ? voltage regulator ....................................................................... 21 ? external vco operation ................................................ 21 ? i 2 c interface ................................................................................ 21 ? spi interface ................................................................................ 23 ? program modes .......................................................................... 25 ? register map ................................................................................... 27 ? register map summary ............................................................. 27 ? register bit descriptions ........................................................... 28 ? suggested power-up sequence ..................................................... 31 ? initial register write sequence ................................................ 31 ? evaluation board ............................................................................ 32 ? general description ................................................................... 32 ? hardware description ............................................................... 32 ? pcb artwork............................................................................... 35 ? bill of materials ........................................................................... 38 ? outline dimensions ....................................................................... 39 ? ordering guide .......................................................................... 39 ? revision history 4/10rev. 0 to rev. a changes to table 5 ............................................................................ 9 changes to lomon outputs section ......................................... 33 changes to ordering guide .......................................................... 39 1/10revision 0: initial version
adrf6750 rev. a | page 3 of 40 specifications v cc = 5 v, t a = 25c, i/q inputs = 0.9 v p-p differential sine waves in quadrature on a 500 mv dc bias, baseband frequency = 1 mhz, refin = 10 mhz, pfd = 20 mhz, loop bandwidth = 50 khz, and lomonx is off, unless otherwise noted. table 1. parameter test conditions/comments min typ max unit rf output rfout pin operating frequency range 950 1575 mhz nominal output power v iq = 0.9 v p-p differential ?1.6 dbm gain flatness any 40 mhz 0.5 db output p1db 8.5 dbm output ip3 f1 bb = 3.5 mhz, f2 bb = 4.5 mhz, p out = ?6 dbm per tone 23 dbm output return loss attenuator setting = 0 db ?12 db lo carrier feedthrough attenuator setting = 0 db to 47 db ?45 dbc 2 lo carrier feedthrough attenuator setting = 0 db to 47 db ?45 dbm sideband suppression ?45 dbc noise floor i/q inputs = 0 v p-p differential, attenuator setting = 0 db ?162 dbm/hz attenuator setting = 0 db to 21 db, carrier offset = 15 mhz ?147 dbc/hz attenuator setting = 21 db to 47 db, carrier offset = 15 mhz ?170 dbm/hz harmonics ?60 dbc reference characteristics refin pin input frequency with r/2 divider enabled 10 300 mhz with r/2 divider disabled 10 165 mhz input sensitivity ac-coupled 0.4 vreg v p-p input capacitance 10 pf input current 100 a charge pump i cp sink/source programmable high value with rset = 4.7 k 5 ma low value 312.5 a absolute accuracy with rset = 4.7 k 4.0 % rset value 4.7 k vco gain k vco 25 mhz/v synthesizer specifications frequency resolution 1 hz spurs integer boundary < loop bandwidth ?55 dbc >10 mhz offset from carrier ?85 dbc phase noise 1 frequency = 950 mhz to 1575 mhz 100 hz offset ?80 dbc/hz 1 khz offset ?88 dbc/hz 10 khz offset ?93 dbc/hz 100 khz offset ?107 dbc/hz 1 mhz offset ?133 dbc/hz >15 mhz offset ?152 dbc/hz integrated phase noise 1 1 khz to 8 mhz integration bandwidth 0.4 rms frequency settling 1 maximum frequency error = 100 hz 170 s maximum frequency step for no autocalibration frequency step with no autocalibration routine; register cr24, bit 0 = 1 100 khz phase detector frequency 10 30 mhz
adrf6750 rev. a | page 4 of 4 0 parameter test conditions/comments min typ max unit gain control gain range 47 db step size 1 db relative step accuracy fixed frequency, adjacent steps all attenuation steps 0.3 db over full frequency range, adjacent steps 1.5 db absolute step accuracy 2 47 db attenuation step ?2.0 db output settling time any step; output power settled to 0.2 db 10 s output disable txdis pin off isolation rf out, attenuator setting = 0 db to 47 db, txdis high ?110 dbm lo, attenuator setting = 0 db to 47 db, txdis high ?90 dbm 2 x lo, attenuator setting = 0 db to 47 db, txdis high ?50 dbm turn-on settling time txdis high to low (90% of envelope) 180 ns turn-off settling time txdis low to high (to ?55 dbm) 270 ns monitor output lomonp, lomonn pins nominal output power ?24 dbm baseband inputs ibbp, ibbn , qbbp, qbbn pins i and q input bias level 500 mv 1 db bandwidth 250 mhz logic inputs input high voltage, v inh cs, txdis pins 1.4 v input low voltage, v inl cs, txdis pins 0.6 v input high voltage, v inh sdi/sda, clk/scl pins 2.1 v input low voltage, v inl sdi/sda, clk/scl pins 1.1 v input current, i inh /i inl cs, txdis, sdi/sda, clk/scl pins 1 a input capacitance, c in cs, txdis, sdi/sda, clk/scl pins 10 pf logic outputs output high voltage, v oh sdo, ldet pins; i oh = 500 a 2.8 v output low voltage, v ol sdo, ldet pins; i ol = 500 a 0.4 v sda (sdi/sda); i ol = 3 ma 0.4 v power supplies vcc1, vcc2, vcc3, vcc4, vreg1, vreg2, vreg3, vreg4, vreg5, vreg6, and regout pins regout normally connected to vreg1, vreg2, vreg3, vreg4, vreg5, and vreg6 voltage range vcc1, vcc2, vcc3, and vcc4 4.75 5 5.25 v regout, vreg1, vreg2, vreg3, vreg4, vreg5, and vreg6 3.3 v supply current vcc1, vcc2, vcc3, and vcc4 combined; regout con- nected to vreg1, vreg2, vreg3, vreg4, vreg5, and vreg6 310 340 ma operating temperature ?40 +85 c 1 lbw = 50 khz at lo = 1200 mhz; i cp = 2.5 ma. 2 all other attenuation steps have an absolute error of <2.0 db.
adrf6750 rev. a | page 5 of 40 timing characteristics i 2 c interface timing table 2. parameter 1 symbol limit unit scl clock frequency f scl 400 khz max scl pulse width high t high 600 ns min scl pulse width low t low 1300 ns min start condition hold time t hd;sta 600 ns min start condition setup time t su;sta 600 ns min data setup time t su;dat 100 ns min data hold time t hd;dat 300 ns min stop condition setup time t su;sto 600 ns min data valid time t vd;dat 900 ns max data valid acknowledge time t vd;ack 900 ns max bus free time t buf 1300 ns min 1 see figure 2. sd a t hd;sta t su;dat start condition stop condition s ss p scl 1/ f scl t high t low t hd;dat t vd;dat and t vd;ack (ack signal only) t buf t su;sto t su;sta 08201-003 figure 2. i 2 c port timing diagram
adrf6750 rev. a | page 6 of 40 spi interface timing table 3. parameter 1 symbol limit unit clk frequency f clk 20 mhz max clk pulse width high t 1 15 ns min clk pulse width low t 2 15 ns min start condition hold time t 3 5 ns min data setup time t 4 10 ns min data hold time t 5 5 ns min stop condition setup time t 6 5 ns min sdo access time t 7 15 ns min cs to sdo high impedance t 8 25 ns max 1 see figure 3. t 1 t 3 cs clk sdi sdo t 6 t 8 t 7 t 2 t 5 t 4 08201-004 figure 3. spi port timing diagram
adrf6750 rev. a | page 7 of 40 absolute maximum ratings table 4. parameter rating supply voltage vcc1, vcc2, vcc3, and vcc4 ?0.3 v to +6 v supply voltage vreg1, vreg2, vreg3, vreg4, vreg5, and vreg6 ?0.3 v to +4 v ibbp, ibbn, qbbp, and qbbn 0 v to 2.5 v digital i/o ?0.3 v to +4 v analog i/o (other than ibbp, ibbn, qbbp, and qbbn) ?0.3 v to +4 v testlo, testlo difference 1.5 v ja (exposed paddle soldered down) 26c/w maximum junction temperature 120c storage temperature range ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
adrf6750 rev. a | page 8 of 40 pin configuration and fu nction descriptions pin 1 indicator 1 vcc4 2 ibbp 3 ibbn 4 qbbn 5 qbbp 6 agnd 7 rset 8 lf3 9 cp 10 lf2 11 vcc1 12 regout 13 vreg1 14 vreg2 35 ccomp3 36 vreg6 37 agnd 38 vtune 39 agnd 40 agnd 41 vcc3 42 vcc3 34 ccomp2 33 ccomp1 32 dgnd 31 vreg5 30 clk/scl 29 sdi/sda 15 vreg3 16 vreg4 17 ref in 19 agnd 21 agn d 20 agnd 22 testlo 23 testlo 24 agnd 25 lo monp 26 lomonn 27 c s 28 sdo 18 ref in 45 txdis 46 agnd 47 agn d 48 rfout 49 agnd 50 agnd 51 agnd 52 agn d 53 agn d 54 agnd 44 ldet 43 muxout top view (not to scale) adrf6750 55 vcc2 56 vcc2 notes 1. connect exposed pad to ground plane vi a a low impedance path. 08201-005 figure 4. pin configuration table 5. pin function descriptions pin no. mnemonic description 11, 55, 56, 41, 42, 1 vcc1 to vcc4 positive power supplies for i/q modulator. apply a 5 v power supply to vcc1, which should be decoupled with power supply decoupling capacito rs. connect vcc2, vcc3, and vcc4 to the same 5 v power supply. 12 regout 3.3 v output supply. drives vreg1, vreg2, vreg3, vreg4, vreg5, and vreg6. 13, 14, 15, 16, 31, 36 vreg1 to vreg6 positive power supplies for pll synthesizer, vco, and serial port. connect these pins to regout (3.3 v) and decouple them separately. 6, 19, 20, 21, 24, 37, 39, 40, 46, 47, 49, 50, 51, 52, 53, 54 agnd analog ground. connect to a low impedance ground plane. 32 dgnd digital ground. connect to the same low impedance ground plane as the agnd pins. 2, 3 ibbp, ibbn differential in-phase baseband inputs. these high impedance inputs must be dc-biased to approx- imately 500 mv dc and should be driven from a low impedance source. nominal characterized ac signal swing is 450 mv p-p on each pin. this results in a differential drive of 0.9 v p-p with a 500 mv dc bias, resulting in a single sideband output power of approximately ?1.6 dbm. these inputs are not self-biased and must be externally biased. 4, 5 qbbn, qbbp differential quadrature baseband inputs. these hi gh impedance inputs must be dc-biased to approximately 500 mv dc and should be driven from a low impedance source. nominal charac- terized ac signal swing is 450 mv p-p on each pin. this results in a differential drive of 0.9 v p-p with a 500 mv dc bias, resulting in a single sideband output power of approximately ?1.6 dbm. these inputs are not self-biased and must be externally biased. 33, 34, 35 ccomp1 to ccomp3 internal compensation nodes. these pins must be decoupled to ground with a 100 nf capacitor. 38 vtune control input to the vco. this voltage deter mines the output frequenc y and is derived from filtering the cp output voltage. 7 rset charge pump current set. connecting a resistor between this pin and ground sets the maximum charge pump output current. the relationship between i cp and r set is as follows: set cpmax r i 5.23 = where r set = 4.7 k and i cp max = 5 ma. 9 cp charge pump output. when enab led, this output provides i cp to the external loop filter, which, in turn, drives the internal vco.
adrf6750 rev. a | page 9 of 40 pin no. mnemonic description 27 cs chip select, cmos input. when cs is high, the data stored in the shift registers is loaded into one of 31 latches. in i 2 c mode, when cs is high, the slave address of the device is 0x60, and when cs is low, the slave address is 0x40. 29 sdi/sda serial data input for spi port /serial data input/output for i 2 c port. in spi mode, this pin is a high impedance cmos data input, and data is loaded in an 8-bit word. in i 2 c mode, this pin is a bidirec- tional port. 30 clk/scl serial clock input for spi/i 2 c port. this serial clock is used to cloc k in the serial data to the registers. this input is a high impedance cmos input. 28 sdo serial data output for spi port. register states can be read back on the sdo data output line. 17 refin reference input. this high impedance cmos input should be ac-coupled. 18 refin reference input bar. this pin should be ei ther grounded or ac -coupled to ground. 48 rfout rf output. single-ended, 50 , internally biased rf output. this pin must be ac-coupled to the load. nominal output power is ?1.6 dbm for a single sideband baseband drive of 0.9 v p-p differ- ential on the i and q inputs (attenuation = minimum). 45 txdis output disable. this pin can be used to disable the rf output. connect to high logic level to disable the output. connect to low logic level for normal operation. 25, 26 lomonp, lomonn differential monitor outputs. these pins provide a replica of the internal local oscillator frequency (1 lo) at four different power levels: ?6 dbm, ?12 dbm, ?18 dbm, and ?24 dbm, approximately. these open-collector outputs must be terminated wi th external resistors to regout. these outputs can be disabled through serial port programming and should be tied to regout if not used. 22, 23 testlo, testlo differential test inputs. these inputs provide an option for an external 2 lo to drive the modulator. this option can be selected by serial port programming. these inputs must be externally dc-biased and should be grounded if not used. 10, 8 lf2, lf3 no connect pins. 44 ldet lock detect. this output pin indicates the state of the pll: a high level indicates a locked condition, whereas a low level indicates a loss of lock condition. 43 muxout muxout. this output is a test output for diagnostic use only. it should be left unconnected by the customer. exposed paddle ep exposed paddle. connect to ground plane via a low impedance path.
adrf6750 rev. a | page 10 of 40 typical performance characteristics v cc = 5 v, t a = 25c, i/q inputs = 0.9 v p-p differential sine waves in quadrature on a 500 mv dc bias, refin = 10 mhz, pfd = 20 mhz, baseband frequency = 1 mhz, lomonx is off, unless otherwise noted. a nominal condition is defined as 25c, 5.00 v, and worst-ca se frequency. a worst-case condition is defined as having the worst-case temperature, supply voltage, and frequency. ?5 ?4 ?3 ?2 ?1 0 1 2 950 1050 1150 1250 1350 1450 1550 1575 output power (dbm) lo frequency (mhz) +25c; 5.00v +85c; 4.75v +85c; 5.25v -40c; 4.75v -40c; 5.25v 0c; 4.75v 0c; 5.25v +70c; 4.75v +70c; 5.25v 08201-105 figure 5. output power vs. lo frequency, supply, and temperature ?3.0 ?3.2 40 35 30 25 20 15 10 5 0 ?2.8 ?2.6 ?2.4 ?2.2 ?2.0 ?1.8 ?1.6 ?1.4 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 occurrence (%) output power (dbm) nominal worst case 08201-106 figure 6. output power distribution at nominal and worst-case conditions ?5 ?4 ?3 ?2 ?1 0 1 500 750 1000 1250 1500 1750 2000 output power (dbm) lo frequency (mhz) 08201-107 figure 7. output power vs. lo fr equency for external vco mode at nominal conditions ?60 ?50 ?40 ?30 ?20 ?10 0 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 1450 1500 1550 1575 sideband suppression (dbc) lo frequency (mhz) +25c; 5.00v +85c; 4.75v +85c; 5.25v ?40c; 4.75v ?40c; 5.25v 0 8201-108 figure 8. sideband suppression vs. lo frequency, supply, and temperature 0 5 10 15 20 25 30 35 ?60.0 ?62.5 ?57.5 ?55.0 ?52.5 ?50.0 ?47.5 ?45.0 ?42.5 ?40.0 ?37.5 ?35.0 ?32.5 occurrence (%) sideband suppression (dbc) nominal worst case 0 8201-109 figure 9. sideband suppression distribution at nominal and worst-case conditions ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ? 40 carrier feedthrough (dbc) lo frequency (mhz) 08201-110 950 1050 1150 1250 1350 1450 1550 1575 figure 10. lo carrier feedthrough vs. attenuation, lo frequency, supply, and temperature
adrf6750 rev. a | page 11 of 40 0 10 20 30 40 50 60 ?75?80 ?70 ?65 ?60 ?55 ?50 ?45 ?40 ?35 ?30 occurence (%) lo carrier feedthrough (dbc) nominal worst-case 08201-111 figure 11. lo carrier feedthrough distribution at nominal and worst-case conditions and attenuation setting ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ? 40 2 lo carrier feedthrough (dbm) lo frequency (mhz) attenuation = 0db attenuation = 12db attenuation = 21db attenuation = 33db attenuation = 47db 0 8201-112 950 1050 1150 1250 1350 1450 1550 1575 figure 12. 2 lo carrier feedthrough vs. attenuation, lo frequency, supply, and temperature ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 ?25 ?20 ?15 ?10 ?5 0 5 10 0.1 1 10 ideal output power ? output power (dbm) output power (dbm) differential input voltage (v p-p) 1db compression point 0 8201-113 figure 13. output p1db compression point at worst-case lo frequency vs. supply and temperature 0 5 10 15 20 25 30 35 40 45 50 7.06.8 7.2 7.4 7.6 7.8 8.0 8.2 8.4 8.6 8.8 9.0 9.2 occurence (%) output p1db (dbm) nominal worst-case 08201-114 figure 14. output p1db compression point distribution at nominal and worst-case conditions 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 1450 1500 1550 output p1db (dbm) lo frequency (mhz) 1575 08201-116 figure 15. output p1db compressi on point vs. lo frequency at nominal conditions 0 5 10 15 20 25 30 35 40 45 21.25 21.00 21.50 21.75 22.00 22.25 22.50 22.75 23.00 23.25 23.50 23.75 24.00 occurence (%) output ip3 (dbm) nominal worst-case 08201-115 figure 16. output ip3 distribution at nominal and worst-case conditions
adrf6750 rev. a | page 12 of 40 20 21 22 23 24 25 26 27 28 29 30 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 1450 1500 1550 1575 lo frequency (mhz) output ip3 intercept point (dbm) 08201-119 figure 17. output ip3 vs. lo frequency at nominal conditions ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ? 60 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 1450 1500 1550 1575 lo off isol a tion (dbm) lo frequency (mhz) attenuation = 0db attenuation = 47db attenuation = 21db 08201-117 figure 18. lo off isolation vs. atte nuation, lo frequency, supply, and temperature ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ? 20 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 1450 1500 1550 1575 2 lo off iso l a tion (dbm) lo frequency (mhz) attenuation = 0db attenuation = 21db attenuation = 47db 08201-118 figure 19. 2 lo off isolation vs. attenuation, lo frequency, supply, and temperature ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ? 40 950 1050 1150 1250 1350 1450 1550 1575 output power (dbc) lo frequency (mhz) upper third harmonic ( f lo +3 f bb ) upper second harmonic ( f lo + 2 f bb ) lower third harmonic ( f lo ?3 f bb ) lower second harmonic ( f lo ?2 f bb ) 08201-128 figure 20. second-order and third-order harmonic distortion vs. lo frequency, supply, and temperature 0 10 20 30 40 50 60 70 80 90 100 ?180 ?176 ?172 ?168 ?164 ?160 ?156 ?152 ?148 ?144 ?140 occurence (%) (dbm/hz) noise floor at 15mhz offset frequency (dbc/hz) attenuation = 21db (dbc/hz) attenuation = 0db (dbc/hz) attenuation = 21db (dbm/hz) attenuation = 47db (dbm/hz) 08201-121 figure 21. noise floor at 15 mhz offset frequency distribution at worst-case conditions and di fferent attenuation settings ?170 ?165 ?160 ?155 ?150 ?145 ? 140 ?25 ?20 ?15 ?10 ?5 0 5 10 noise floor (dbm/hz) output power (dbm) 08201-120 figure 22. noise floor at 0 db attenuation vs. output power at nominal conditions
adrf6750 rev. a | page 13 of 40 ?5 ?3 ?1 ?4 ?2 0 1 1 10m 100m 1g normalized output power (db) i and q baseband input frequency (hz) 08201-141 figure 23. normalized i and q input bandwidth ?30 ?25 ?20 ?15 ?10 ?5 0 500 750 1000 1250 1500 1750 2000 s22 (db) output frequency (mhz) attenuation = 0db attenuation = 21db and 47db 08201-150 figure 24. output return loss at worst-case attenuation vs. lo frequency, supply, and temperature 90 80 70 60 50 40 30 20 10 0 1195 1196 1197 1198 1199 1200 1201 1202 1203 1204 1205 rf output (dbm) lo frequency (mhz) lower sideband carrier feedthrough suppressed sideband third harmonic second harmonic 08201-122 figure 25. rf output spectral plot over a 10 mhz span ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 1150 1170 1190 1210 1230 1250 rf output (dbm) lo frequency (mhz) 08201-123 lower sideband carrier feedthrough suppressed sideband third harmonic lower and upper second harmonics figure 26. rf output spectral plot over a 100 mhz span ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 012345 frequency (mhz) power (dbm) 678910 3 lo harmonic 4 lo harmonic 2 lo harmonic lower sideband 5 lo harmonic 8 lo harmonic 08201-124 figure 27. rf output spectral plot over a wide span ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ? 60 100 1k 10k 100k 1m 1 0m 100m phase noise (dbc/hz) offset frequency (hz) 08201-129 figure 28. phase noise performance vs. lo frequency, supply, and temperature
adrf6750 rev. a | page 14 of 4 0 ?160 ?150 ?140 ?130 ?120 ?110 ?100 ?90 ?80 ?70 ? 60 100 1k 10k 100k 1m 10m 100m phase noise (dbc/hz) offset frequency (hz) 08201-130 figure 29. phase noise performance distribution at worst-case conditions ?70 ?65 ?60 ?55 ?50 ?45 ? 40 integer bound a r y spur (dbc) lo frequency (mhz) +25c; 5.00v +85c; 4.75v +85c; 5.25v ?40c; 4.75v ?40c; 5.25v 0 8201-125 950 1050 1150 1250 1350 1450 1550 1575 figure 30. integer boundary spur performance vs. lo frequency, supply, and temperature 0 10 20 30 40 50 60 70 80 ?80 ?75 ?70 ?65 ?60 ?55 ?50 ?45 ?40 occurence (%) integer boundary spurs (dbc) nominal worst case 08201-126 ?85 figure 31. integer boundary spur distribution at nominal and worst-case conditions ?120 ?110 ?100 ?90 ?80 ?70 ? 60 900 1000 1100 1200 1300 1400 1500 1600 1625 spurs > 10mhz offset frequency (dbc) lo frequency (mhz) pfd spurs at 20mhz offset reference spurs at 10mhz offset 08201-127 figure 32. spurs > 10 mhz from carrier vs. lo frequency, supply, and temperature 0 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 1450 1500 1550 1575 rms jitter (degrees) lo frequency (mhz) 08201-131 figure 33. integrated phase noise vs. lo frequency at nominal conditions 0 10 20 30 40 50 60 0.300 0.275 0.325 0.350 0.375 0.400 0.425 0.450 0.475 0.500 occurence (%) rms jitter (degrees) nominal worst case 08201-137 figure 34. integrated phase noise at nominal and worst-case conditions
adrf6750 rev. a | page 15 of 40 0.1 1 10 100 1k 10k 100k 1m 10m 100m 1g ?50 ?25 0 25 50 75 100 125 150 175 200 225 250 frequency error (hz) time (s) cr23[3] = 1 cr23[3] = 0 ldet ldet acquisition to 100hz start of acquisition on cr0 write 08201-132 figure 35. pll frequency settling ti me at worst-case low frequency with lock detect shown ?50 ?45 ?40 ?35 ?30 ?25 ?20 ?15 ?10 ?5 0 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 1450 1500 1550 1575 ouptut power (dbm) lo frequency (mhz) 08201-133 figure 36. attenuator gain vs. lo frequency by gain code, all attenuator code steps ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 1450 1500 1550 1575 a ttenu a tor rel a tive step accurac y (db) lo frequency (mhz) 0 8201-134 figure 37. attenuator relative step accuracy over all attenuation steps vs. lo frequency, nominal conditions 0 5 10 15 20 25 30 35 40 45 50 ?0.8 ?1.0 ?0.6 ?0.4 ?0.2 0 attenuator relative step accuracy (db) 0.2 0.4 0.6 0.8 1.0 occurence (%) nominal worst case 08201-135 figure 38. attenuator relative step accuracy distribution at nominal and worst-case conditions 0 5 10 15 20 25 30 35 40 45 50 ?2.00 ?2.25 ?1.75 ?1.50 ?1.25 ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.25 occurence (%) 08201-140 attenuator relative step accuracy across full output frequency range (db) nominal worst case figure 39. attenuator relative step accuracy across full output frequency range distribution at nominal and worst-case conditions ?1.5 ?1.3 ?0.9 ?1.1 ?0.7 ?0.5 ?0.1 ?0.3 0.1 0.5 0.3 500 600 800 700 900 1000 1100 1300 1200 1400 1500 1600 1700 1800 1900 2000 a ttenu a tor rel a tive step accurac y (db) lo frequency (mhz) 0 8201-136 figure 40. attenuator relative step accuracy over all attenuation steps vs. lo frequency for external vco mode, nominal conditions
adrf6750 rev. a | page 16 of 40 ?3.0 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 1450 1500 1550 1575 a ttenu a tor absolute step accuracy (db) lo frequency (mhz) 08201-139 figure 41. attenuator absolute step accuracy over all attenuation steps vs. lo frequency, nominal conditions 0 10 20 30 40 50 60 70 ?3.2 ?3.4 ?3.0 ?2.8 ?2.6 ?2.4 ?2.2 ?2.0 ?1.8 ?1.6 ?1.4 ?1.2 ?1.0 ?0.8 ?0.6 ?0.4 occurence (%) 08201-138 attenuator absolute step accuracy (db) nominal worst case figure 42. attenuator absolute step accuracy distribution at nominal and worst-case conditions ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 500 600 700 800 900 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 a ttenu a tor absolute step accuracy (db) lo frequency (mhz) 08201-142 figure 43. attenuator absolute step accuracy over all attenuation steps vs. lo frequency for external vco mode, nominal conditions 1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 950 1000 1050 1100 1150 1200 1250 1300 1350 1400 1450 1500 1550 1575 gain fl a tness in any 40mhz (db) lo frequency (mhz) 08201-149 figure 44. gain flatness in any 40 mhz for all attenuation steps vs. lo frequency at nominal conditions 0 0.5 1.0 1.5 1db to 6db attenuator step sizes increasing step size settling time (s) 2.0 2.5 3.0 3.5 4.0 4.5 5.0 settling time to 0.2db settling time to 0.5db 08201-143 figure 45. attenuator settling time to 0.2 db and 0.5 db for small steps (1 db to 6 db) at nominal conditions 0 2 4 6 8 10 12 14 16 18 20 settling time to 0.2db settling time to 0.5db 7db to 47db attenuator step sizes 08201-144 increasing step size settling time (s) figure 46. attenuator settling time to 0.2 db and 0.5 db for large steps (7 db to 47 db) at nominal conditions
adrf6750 rev. a | page 17 of 40 0 10 20 30 40 50 60 70 80 90 100 0.5 0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 occurence (%) attenuator settling time (s) nominal settling time to 0.2db nominal settling time to 0.5db worst-case settling time to 0.2db worst-case settling time to 0.5db 08201-146 figure 47. attenuator settling time to 0.2 db and 0.5 db distribution at nominal and worst-case cond itions for typical small step 0 10 20 30 40 50 60 70 80 90 100 2 0 4 6 8 10 12 14 16 18 20 occurence (%) attenuator settling time (s) nominal settling time to 0.2db nominal settling time to 0.5db worst-case settling time to 0.2db worst-case settling time to 0.5db 08201-145 figure 48. attenuator settling time to 0.2 db and 0.5 db distribution at nominal and worst-case conditio ns for worst-case small step (36 db to 42 db) 0 10 20 30 40 50 60 70 80 90 100 2 0 4 6 8 10 12 14 16 18 20 occurence (%) attenuator settling time (s) nominal settling time to 0.2db nominal settling time to 0.5db worst-case settling time to 0.2db worst-case settling time to 0.5db 08201-147 figure 49. attenuator settling time to 0.2 db and 0.5 db distribution at nominal and worst-case conditions for typical large step (0 db to 47 db) 0 10 20 30 40 50 60 70 80 3 0 6 9 12151821242730 occurence (%) attenuator settling time (s) nominal settling time to 0.2db nominal settling time to 0.5db worst-case settling time to 0.2db worst-case settling time to 0.5db 08201-148 figure 50. attenuator settling time to 0.2 db and 0.5 db distribution at nominal and worst-case conditions for worst-case large step (47 db to 0 db) ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 0 0.51.01.52.02.53.03.54.04.55.0 output power (dbm) txdis settling time (s) 08201-151 txdis turn-on = 180ns turn-off = 270ns figure 51. txdia turn-on settling time at worst-case supply and temperature
adrf6750 rev. a | page 18 of 40 theory of operation 2 doubler 5-bit r-divider from refin pin to pfd 2 08201-008 overview t he adrf6750 device can be divided into the following basic building blocks: figure 53. reference input path the pfd frequency equation is ? pll synthesizer and vco f pfd = f refin [(1 + d )/( r (1 + t ))] (2) ? quadrature modulator ? attenuator where: f refin is the reference input frequency. d is the doubler bit. r is the programmed divide ratio of the binary 5-bit programmable reference divider (1 to 32). t is the divide-by-2 bit (0 or 1). ? volt age regu l ator ? i 2 c/spi interface each of these building blocks is described in detail in the sections that follow. pll synthesizer and vco rf fractional-n divider overview the rf fractional-n divider allows a division ratio in the pll feedback path that can range from 23 to 4095. the relationship between the fractional-n divider and the lo frequency is described in the following section. the phase-locked loop (pll) consists of a fractional-n frequency synthesizer with a 25-bit fixed modulus, allowing a frequency resolution of less than 1 hz over the entire frequency range. it also has an integrated voltage-controlled oscillator (vco) with a fundamental output frequency ranging from 1900 mhz to 3150 mhz. this allows the pll to generate a stable frequency at 2 lo, which is then divided down to provide a local oscillator (lo) frequency ranging from 950 mhz to 1575 mhz to the quadrature modulator. int and frac relationship the integer (int) and fractional (frac) values make it possible to generate output frequencies that are spaced by fractions of the phase frequency detector (pfd) frequency. see the examplechanging the lo frequency section for more information. reference input section the lo frequency equation is the reference input stage is shown in figure 52 . sw1 and sw2 are normally closed switches. sw3 is normally open. when power-down is initiated, sw3 is closed, and sw1 and sw2 are open. this ensures that there is no loading of the refin pin at power-down. lo = f pfd ( int + ( frac /2 25 )) (1) where: lo is the local oscillator frequency. f pfd is the pfd frequency. int is the integer component of the required division factor and is controlled by the cr6 and cr7 registers. frac is the fractional component of the required division factor and is controlled by the cr0 to cr3 registers. buffer to r-divider refin 100k ? nc sw2 sw3 nc nc sw1 power-down control 08201-006 n-counter int reg to pfd rf n-divider n = int + frac/2 25 from vco output dividers frac value third-order fractional interpolator 0 8201-007 figure 52. reference input stage reference input path the on-chip reference frequency doubler allows the input reference signal to be doubled. this is useful for increasing the pfd comparison frequency. making the pfd frequency higher improves the noise performance of the system. doubling the pfd frequency usually improves the in-band phase noise performance by 3 dbc/hz. figure 54. rf fractional-n divider phase frequency detector (pfd) and charge pump the pfd takes inputs from the r-divider and the n-counter and produces an output proportional to the phase and frequency differ- ence between them (see figure 55 for a simplified schematic). the pfd includes a fixed delay element that sets the width of the antibacklash pulse, ensuring that there is no dead zone in the pfd transfer function. the 5-bit r-divider allows the input reference frequency (ref in ) to be divided down to produce the reference clock to the pfd. division ratios from 1 to 32 are allowed. an additional divide-by-2 function in the reference input path allows for a greater division range.
adrf6750 rev. a | page 19 of 40 u3 clr2 q2 d2 u2 down up hi hi cp ?in +in charge pump delay clr1 q1 d1 u1 08201-009 figure 55. pfd simplified schematic lock detect (ldet) ldet (pin 44) signals when the pll has achieved lock to an error frequency of less than 100 hz. on a write to register cr0, a new pll acquisition cycle starts, and the ldet signal goes low. when lock has been achieved, this signal returns high. voltage-controlled oscillator (vco) the vco core in the adrf6750 consists of two separate vcos, each with 16 overlapping bands. figure 56 shows an acquisition plot demonstrating both the vco overlap at roughly 1260 mhz and the multiple overlapping bands within each vco. the choice of two 16-band vcos allows a wide frequency range to be covered without a large vco sensitivity (k vco ) and resultant poor phase noise and spurious performance. note that the vco range is larger than the 2 lo frequency range of the part to ensure that the device has enough margin to cover the full frequency range over all conditions. 0.5 0.7 0.9 1.1 1.3 1.5 1.7 1.9 2.1 2.3 2.5 800 900 1000 1100 1200 1300 1400 1500 1600 1700 lo frequency (mhz) vtune (v) 08201-057 figure 56. v tune vs. lo frequency the correct vco and band are chosen automatically by the vco and band select circuitry when register cr0 is updated. this is referred to as autocalibration. the autocalibration time is set to 50 s. during this time, the vco v tune is disconnected from the output of the loop filter and is connected to an internal reference voltage. a typical frequency acquisition is shown in figure 57 . 10 100 1k 10k 100k 1m 10m 100m 1 g 0 20 40 60 80 100 120 140 160 180 200 220 240 260 280 300 frequency error (hz) time (s) autocal time (s) acquisition to 100hz 08201-158 figure 57. pll acquisition after autocalibration, normal pll action resumes and the correct frequency is acquired to within a frequency error of 100 hz in 170 s typically. for a maximum cumulative step of 100 khz, autocalibration can be turned off by register cr24, bit 0. this enables cumu- lative pll acquisitions of 100 khz or less to occur without the autocalibration procedure, which improves acquisition times significantly (see figure 58 ). 10 100 1k 10k 100k 0 50 100 150 200 frequency error (hz) time (s) acquisition to 100hz 08201-159 figure 58. pll acquisition without autocalibration for 100 khz step the vco displays a variation of k vco as v tune varies within the band and from band to band. figure 59 shows how the k vco varies across the full lo frequency range. also shown is the average value for each of the frequency bands. figure 59 is useful when calculating the loop filter bandwidth and individual loop filter components.
adrf6750 rev. a | page 20 of 40 0 5 10 15 20 25 30 35 40 950 1050 1150 1250 1350 1450 1550 1575 lo frequency (mhz) vco sensitivity (mhz/v) 08201-160 figure 59. k vco vs. lo frequency quadrature modulator overview a basic block diagram of the adrf6750 quadrature modulator circuit is shown in figure 60 . the vco generates a signal at the 2 lo frequency, which is then divided down to give a signal at the lo frequency. this signal is then split into in-phase and quadrature components to provide the lo signals that drive the mixers. vco v -to-i v-to-i ib b p ibbn qbbp qbbn balun rfout to a ttenuator quad phase splitter 2 08201-012 figure 60. block diagram of the quadrature modulator the i and q baseband input signals are converted to currents by the v-to-i stages, which then drive the two mixers. the outputs of these mixers combine to feed the output balun, which provides a single-ended output. this single-ended output is then fed to the attenuator and, finally, to the external rfout signal pin. baseband inputs the baseband inputs, qbbp, qbbn, ibbp, and ibbn, must be driven from a differential source. the nominal drive level of 0.9 v p-p differential (450 mv p-p on each pin) should be biased to a common-mode level of 500 mv dc. to set the dc bias level at the baseband inputs, refer to figure 61 . the average output current on each of the ad9779 outputs is 10 ma. a current of 10 ma flowing through each of the 50 resistors to ground produces the desired dc bias of 500 mv at each of the baseband inputs. 50 ? 50 ? 50 ? 50 ? ibbp ibbn qbbn qbbp out1_p out1_n out2_n out2_p adrf6750 current output dac (example: ad9779) 08201-013 figure 61. establishing dc bi as level on baseband inputs the differential baseband inputs (qbbp, qbbn, ibbn, and ibbp) consist of the bases of pnp transistors, which present a high impedance of about 30 k in parallel with roughly 2 pf of capacitance. the impedance looks like 30 k below 1 mhz and starts to roll off at higher frequency. a 100 differential termination is recommended at the baseband inputs, and this dominates the input impedance as seen by the input baseband signal. this ensures that the input impedance, as seen by the input circuit, remains flat across the baseband bandwidth. see figure 62 for a typical configuration. 50 ? 50 ? 100 ? 100 ? 50 ? 50 ? ibbp ibbn qbbn qbbp out1_p out1_n out2_n out2_p adrf6750 current output dac (example: ad9779) low- pass filter low- pass filter 08201-014 figure 62. typical baseband input configuration the swing of the ad9779 output currents ranges from 0 ma to 20 ma. the ac voltage swing is 1 v p-p single-ended or 2 v p-p differential with the 50 resistors in place. the 100 differen- tial termination resistors at the baseband inputs have the effect of limiting this swing without changing the dc bias condition of 500 mv. the low-pass filter is used to filter the dac outputs and remove images when driving a modulator. another consideration is that the baseband inputs actually source a current of 240 a out of each of the four inputs. this current must be taken into account when setting up the dc bias of 500 mv. in the initial example based on figure 61 , an error of 12 mv occurs due to the 240 a current flowing through the 50 resistor. analog devices, inc., recommends that the accuracy of the dc bias should be 500 mv 25 mv. it is also important that this 240 a current have a dc path to ground.
adrf6750 rev. a | page 21 of 40 optimization the carrier feedthrough and the sideband suppression perfor- mance of the adrf6750 can be improved over the numbers specified in table 1 by using the following optimization techniques. carrier feedthrough nulling carrier feedthrough results from dc offsets that occur between the p and n inputs of each of the differential baseband inputs. normally these inputs are set to a dc bias of approximately 500 mv. however, if a dc offset is introduced between the p and n inputs of either or both i and q inputs, the carrier feedthrough is affected in either a positive or a negative fashion. note that the dc bias level remains at 500 mv (average p and n level). the i channel offset is often held constant while the q channel offset is varied until a minimum carrier feedthrough level is obtained. then, while retaining the new q channel offset, the i channel offset is adjusted until a new minimum is reached. this is usually per- formed at a single frequency and, thus, is not optimized over the complete frequency range. multiple optimizations at different frequencies must be performed to ensure optimum carrier feed- through across the full frequency range. sideband suppression nulling sideband suppression results from relative gain and relative phase offsets between the i channel and q channel and can be optimized through adjustments to those two parameters. adjusting only one parameter improves the sideband suppression only to a point. for optimum sideband suppression, an iterative adjustment between phase and amplitude is required. attenuator the digital attenuator consists of six attenuation blocks: 1 db, 2 db, 4 db, 8 db, and two 16 db blocks; each is separately controlled. each attenuation block consists of field effect transistor (fet) switches and resistors that form either a pi- shaped or a t-shaped attenuator. by controlling the states of the fet switches through the control lines, each attenuation block can be set to the pass state (0 db) or the attenuation state (n db). the various combinations of the six blocks provide the attenuation states from 0 db to 47 db in 1 db increments. voltage regulator the voltage regulator is powered from a 5 v supply that is provided by vcc1 (pin 11) and produces a 3.3 v nominal regulated output voltage, regout, on pin 12. this pin must be connected (external to the ic) to the vreg1 through vreg6 package pins. the regulator output (regout) should be decoupled by a parallel combination of 10 pf and 220 f capacitors. the 220 f capacitor, which is recommended for best performance, decouples broadband noise, leading to better phase noise. each vregx pin should have the following decoupling capacitors: 100 nf multilayer ceramic with an additional 10 pf in parallel, both placed as close as possible to the dut power supply pins. x7r or x5r capacitors are recommended. see the evaluation board section for more information. external vco operation th e adrf6750 can be operated with an external vco. this can be useful if the user wants to improve the phase noise performance or extend the frequency range. note that the external vco needs to operate at a frequency of 2 lo. to operate the adrf6750 with an external vco, follow these steps: 1. connect the charge pump output (pin 9) to the loop filter and onward to the external vco input. the k vco of the external vco needs to be taken into account when calculating the loop bandwidth and loop filter components. note that a 50 khz loop bandwidth is recommended when using the internal vco. this takes into account the phase noise performance of the internal vco. it is possible for an external vco to provide better phase noise performance and a 50 khz loop bandwidth may not be optimal in that case. when selecting a loop bandwidth, consider rms jitter, phase noise performance, and acquisition time. adisimpll? can be used to optim- ize the loop bandwidth with a variety of external vcos. 2. connect the output of the external vco to the testlo and testlo input pins. it is likely that a low-pass filter will be needed to filter the output of the external vco. this is very important if the external vco has poor second harmonic performance. second harmonic performance directly impacts sideband suppression performance. for example, ?30 dbc second harmonic performance leads to ?30 dbc sideband suppres- sion. both testlo and testlo need to be dc biased. a dc bias of 1.7 v to 3.3 v is recommended. the regout output provides a 3.3 v output voltage. 3. select external vco operation by setting the following bits: ? set register cr27[3] = 1. this bit multiplexes the testlo and testlo through to the quadrature modulator. ? s et register cr28[5] = 1. this bit powers down the internal vco and connects the external vco to the pll. 4. set the correct polarity for the pfd based on the slope of the k vco . the default is for positive polarity. this bit is accessed by register cr12[3]. when selecting an external vco, at times it is difficult to select one with an appropriate frequency range and k vco . one solu- tion may be the adf4350, which can function as vco only with a range of 137.5 mhz to 4.4 ghz. note that the adf4350 requires an autocalibration time of 100 s which directly impacts acquisition time. i 2 c interface the adrf6750 supports a 2-wire, i 2 c-compatible serial bus that drives multiple peripherals. the serial data (sda) and serial
adrf6750 rev. a | page 22 of 40 clock (scl) inputs carry information between any devices that are connected to the bus. each slave device is recognized by a unique address. the adrf6750 has two possible 7-bit slave addresses for both read and write operations. the msb of the 7-bit slave address is set to 1. bit 5 of the slave address is set by the cs pin (pin 27). bits[4:0] of the slave address are set to all 0s. the slave address consists of the seven msbs of an 8-bit word. the lsb of the word sets either a read or a write oper- ation (see figure 63 ). logic 1 corresponds to a read operation, whereas logic 0 corresponds to a write operation. to control the device on the bus, the following protocol must be followed. the master initiates a data transfer by establishing a start condition, defined by a high-to-low transition on sda while scl remains high. this indicates that an address/data stream follows. all peripherals respond to the start condition and shift the next eight bits (the 7-bit address and the r/w bit). the bits are transferred from msb to lsb. the peripheral that recognizes the transmitted address responds by pulling the data line low during the ninth clock pulse. this is known as an acknowledge bit. all other devices then withdraw from the bus and maintain an idle condition. during the idle condition, the device monitors the sda and scl lines waiting for the start condition and the correct transmitted address. the r/w bit determines the direction of the data. logic 0 on the lsb of the first byte indicates that the master writes information to the peripheral. logic 1 on the lsb of the first byte indicates that the master reads information from the peripheral. the adrf6750 acts as a standard slave device on the bus. the data on the sda pin (pin 29) is eight bits long, supporting the 7-bit addresses plus the r/w bit. the adrf6750 has 34 subad- dresses to enable the user-accessible internal registers. therefore, it interprets the first byte as the device address and the second byte as the starting subaddress. autoincrement mode is supported, which allows data to be read from or written to the starting sub- address and each subsequent address without manually addressing the subsequent subaddress. a data transfer is always terminated by a stop condition. the user can also access any unique subaddress register on a one-by-one basis without updating all registers. stop and start conditions can be detected at any stage of the data transfer. if these conditions are asserted out of sequence with normal read and write operations, they cause an immediate jump to the idle condition. if an invalid subaddress is issued by the user, the adrf6750 does not issue an acknowledge and returns to the idle condition. in a no acknowledge condition, the sda line is not pulled low on the ninth pulse. see figure 64 and figure 65 for sample write and read data transfers, figure 66 for the timing protocol, and figure 2 for a more detailed timing diagram. 1a500000x msb = 1 set by pin 27 (cs) 0 = wr 1 = rd slave address[6:0] r/w ctrl 08201-016 figure 63. slave address configuration s slave addr, lsb = 0 (wr) a(s) a(s) a(s) data subaddr a(s) p data s = start bit p = stop bit a(s) = acknowledge by slave 0 8201-017 figure 64. i 2 c write data transfer s s = start bit p = stop bit a(s) = acknowledge by slave a(m) = acknowledge by master a(m) = no acknowledge by master s slave addr, lsb = 0 (wr) slave addr, lsb = 1 (rd) a(s) a(s) subaddr a(s) data a(m) data p a(m) 08201-018 figure 65. i 2 c read data transfer start bit s stop bit p ack ack wr ack d0 d7 a0 a7 a5 a6 slave addr[4:0] slave address subaddress data subaddr[6:1] data[6:1] scl sda 08201-002 figure 66. i 2 c data transfer timing
adrf6750 rev. a | page 23 of 40 spi interface the adrf6750 also supports the spi protocol. the part powers up in i 2 c mode but is not locked in this mode. to stay in i 2 c mode, it is recommended that the user tie the cs line to either 3.3 v or gnd, thus disabling spi mode. it is not possible to lock the i 2 c mode, but it is possible to select and lock the spi mode. to select and lock the spi mode, three pulses must be sent to the cs pin, as shown in figure 67 . when the spi protocol is locked in, it cannot be unlocked while the device is still powered up. to reset the serial interface, the part must be powered down and powered up again. serial interface selection the cs pin controls selection of the i 2 c or spi interface. figure 67 shows the selection process that is required to lock the spi mode. to communicate with the part using the spi protocol, three pulses must be sent to the cs pin. on the third rising edge, the part selects and locks the spi protocol. consistent with most spi standards, the cs pin must be held low during all spi communication to the part and held high at all other times. spi serial interface functionality the spi serial interface of the adrf6750 consists of the cs, sdi (sdi/sda), clk (clk/scl), and sdo pins. cs is used to select the device when more than one device is connected to the serial clock and data lines. clk is used to clock data in and out of the part. the sdi pin is used to write to the registers. the sdo pin is a dedicated output for the read mode. the part operates in slave mode and requires an externally applied serial clock to the clk pin. the serial interface is designed to allow the part to be interfaced to systems that provide a serial clock that is synchronized to the serial data. figure 68 shows an example of a write operation to the adrf6750. data is clocked into the registers on the rising edge of clk using a 24-bit write command. the first eight bits represent the write command 0xd4, the next eight bits are the register address, and the final eight bits are the data to be written to the specific register. figure 69 shows an example of a read operation. in this example, a shortened 16-bit write command is first used to select the appropriate register for a read operation, the first eight bits representing the write command 0xd4 and the final eight bits representing the specific register. then the cs line is pulsed low for a second time to retrieve data from the selected register using a 16-bit read command, the first eight bits representing the read command 0xd5 and the final eight bits representing the contents of the register being read. figure 3 shows the timing for both spi read and spi write operations. spi locked on third rising edge spi framing edge c b a spi locked on third rising edge spi framing edge c b a cs (starting high) cs (starting low) 08201-019 figure 67. selecting the spi protocol
adrf6750 rev. a | page 24 of 40 register address write command [0xd4] ??? ??? ??? start cs clk sdi d7d6d5d4d3d2d1d0 d0 d7 d6 d5 d4 d3 d2 d1 ? ? ? ? ? ? ? ? ? data byte stop cs (continued) clk (continued) sdi (continued) d7 d6 d5 d4 d3 d2 d1 d0 08201-020 figure 68. spi byte write example register address write command [0xd4] start data byte read command [0xd5] start stop cs clk sdi cs clk sdi sdo d7 d6 d5 d4 d3 d2 d1 d0 d0 d7 d6 d5 d4 d3 d2 d1 d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 x xxxxxxx x xxxxxxx ? ? ? ? ? ? ? ? ? 0 8201-021 figure 69. spi byte read example
adrf6750 rev. a | page 25 of 40 program modes the adrf6750 has 34 8-bit registers to allow program control of a number of functions. either an spi or an i 2 c interface can be used to program the register set. for details about the interfaces and timing, see figure 63 to figure 69 . the registers are documented in table 6 to table 24 . several settings in the adrf6750 are double-buffered. these settings include the frac value, the int value, the 5-bit r-divider value, the reference frequency doubler, the r/2 divider, and the charge pump current setting. this means that two events must occur before the part uses a new value for any of the double-buffered settings. first, the new value is latched into the device by writing to the appropriate register. next, a new write must be performed on register cr0. when register cr0 is written, a new pll acquisition takes place. for example, updating the fractional value involves a write to register cr3, register cr2, register cr1, and register cr0. register cr3 should be written to first, followed by register cr2 and register cr1 and, finally, register cr0. the new acquisition begins after the write to register cr0. double buffering ensures that the bits written to do not take effect until after the write to register cr0. 12-bit integer value register cr7 and register cr6 program the integer value (int) of the feedback division factor. the int value is a 12-bit number whose msbs are programmed through register cr7, bits[3:0]. the lsbs are programmed through register cr6, bits[7:0]. the int value is used in equation 1 to set the lo frequency. note that these registers are double-buffered. 25-bit fractional value register cr3 to register cr0 program the fractional value (frac) of the feedback division factor. the frac value is a 25-bit number whose msb is programmed through register cr3, bit 0. the lsb is programmed through register cr0, bit 0. the frac value is used in equation 1 to set the lo frequency. note that these registers are double-buffered. reference input path the reference input path consists of a reference frequency doubler, a 5-bit reference divider, and a divide-by-2 function (see figure 53 ). the doubler is programmed through register cr10, bit 5. the 5-bit divider is enabled by programming register cr5, bit 4, and the division ratio is programmed through register cr10, bits[4:0]. the r/2 divider is programmed through register cr10, bit 6. note that these registers are double-buffered. when using a 10 mhz reference input frequency, enable the doubler and disable the 5-bit divider and divide-by-2 to ensure a pfd frequency of 20 mhz. as mentioned in the reference input path section, making the pfd frequency higher improves the system noise performance. charge pump current register cr9, bits[7:4], specify the charge pump current setting. with an r set value of 4.7 k, the maximum charge pump current is 5 ma. the following equation applies: i cpmax = 23.5/ r set the charge pump current has 16 settings from 312.5 a to 5 ma. for the loop filter that is specified in the application solution, a charge pump current of 2.5 ma (register cr9[7:4] = 7) gives a loop bandwidth of 50 khz, which is the recommended loop bandwidth setting. transmit disable control (txdis) the transmit disable control (txdis) is used to disable the rf out- put. txdis is normally held low. when asserted (brought high), it disables the rf output. register cr14 is used to control which circuit blocks are powered down when txdis is asserted. to meet both the off isolation power specifications and the turn-on/ turn-off settling time specifications, a value of 0x1b should be loaded into register cr14. this effectively ensures that the attenuator is always enabled when txdis is asserted, even if other circuitry is disabled. power-down/power-up control bits th e three programmable power-up and power-down control bits are as follows: ? register cr12, bit 2. master power control bit for the pll, including the vco. this bit is normally set to a default value of 0 to power up the pll. ? register cr27, bit 2. controls the lo monitor outputs, lomonp and lomonn. the default is 0 when the monitor outputs are powered down. setting this bit to 1 powers up the monitor outputs to one of ?6 dbm, ?12 dbm, ?18 dbm, or ?24 dbm, as controlled by register cr27, bits[1:0]. ? register cr29, bit 0. controls the quadrature modulator power. the default is 0, which powers down the modulator. write a 1 to this bit to power up the modulator. lock detect (ldet) lock detect is enabled by setting register cr23, bit 4, to 1. register cr23, bit 3 sets the number of up/down pulses generated by the pfd before lock detect is declared. the default is 3072 pulses, which is selected when bit 3 is set to 0. a more aggressive setting of 2048 is selected when bit 3 is set to 1. this improves the lock detect time by 50 s. note, however, that it does not affect the acquisition time to 100 hz. register cr23, bit 2 should be set to 0 for best operation. this bit sets up the pfd up/down pulses to a coarse or low precision setting.
adrf6750 rev. a | page 26 of 40 vco autocalibration the vco uses an autocalibration technique to select the correct vco and band, as explained in the volt age - c ont rol le d os ci l l ator (vco) section. register cr24, bit 0, controls whether the auto- calibration is enabled. for normal operation, autocalibration needs to be enabled. however, if using cumulative frequency steps of 100 khz or less, autocalibration can be disabled by setting this bit to 1 and then a new acquisition is initiated by writing to register cr0. attenuator the attenuator can be programmed from 0 db to 47 db in steps of 1 db. control is through register cr30, bits[5:0]. revision readback the revision of the silicon die can be read back via register cr33.
adrf6750 rev. a | page 27 of 40 register map register map summary table 6. register map summary register address (hex) register name type description 0x00 cr0 read/write fractional word 4 0x01 cr1 read/write fractional word 3 0x02 cr2 read/write fractional word 2 0x03 cr3 read/write fractional word 1 0x04 cr4 read/write reserved 0x05 cr5 read/write 5-bit reference divider enable 0x06 cr6 read/write integer word 2 0x07 cr7 read/write integer word 1 and muxout control 0x08 cr8 read/write reserved 0x09 cr9 read/write charge pump current setting 0x0a cr10 read/write reference frequency control 0x0b cr11 read/write reserved 0x0c cr12 read/write pll power-up 0x0d cr13 read/write reserved 0x0e cr14 read/write txdis control 0x0f cr15 read/write reserved 0x10 cr16 read/write reserved 0x11 cr17 read/write reserved 0x12 cr18 read/write reserved 0x13 cr19 read/write reserved 0x14 cr20 read/write reserved 0x15 cr21 read/write reserved 0x16 cr22 read/write reserved 0x17 cr23 read/write lock detector control 0x18 cr24 read/write autocalibration 0x19 cr25 read/write reserved 0x1a cr26 read/write reserved 0x1b cr27 read/write lo monitor output and external vco control 0x1c cr28 read/write internal vco power-down 0x1d cr29 read/write modulator 0x1e cr30 read/write attenuator 0x1f cr31 read only reserved 0x20 cr32 read only reserved 0x21 cr33 read only revision code
adrf6750 rev. a | page 28 of 40 register bit descriptions table 7. register cr0 (address 0x00), fractional word 4 bit description 1 7 fractional word f7 6 fractional word f6 5 fractional word f5 4 fractional word f4 3 fractional word f3 2 fractional word f2 1 fractional word f1 0 fractional word f0 (lsb) 1 double-buffered. loaded on the write to register cr0. table 8. register cr1 (address 0x01), fractional word 3 bit description 1 7 fractional word f15 6 fractional word f14 5 fractional word f13 4 fractional word f12 3 fractional word f11 2 fractional word f10 1 fractional word f9 0 fractional word f8 1 double-buffered. loaded on the write to register cr0. table 9. register cr2 (address 0x02), fractional word 2 bit description 1 7 fractional word f23 6 fractional word f22 5 fractional word f21 4 fractional word f20 3 fractional word f19 2 fractional word f18 1 fractional word f17 0 fractional word f16 1 double-buffered. loaded on the write to register cr0. table 10. register cr3 (address 0x03), fractional word 1 bit description 7 reserved 6 reserved 5 reserved 4 reserved 3 reserved 2 reserved 1 reserved 0 fractional word f24 (msb) 1 1 double-buffered. loaded on the write to register cr0. table 11. register cr5 (address 0x05), 5-bit reference divider enable bit description 7 reserved 6 reserved 5 reserved 4 5-bit r-divider enable 1 0 = disable 5-bit r-divider (default) 1 = enable 5-bit r-divider 3 reserved 2 reserved 1 reserved 0 reserved 1 double-buffered. loaded on the write to register cr0. table 12. register cr6 (address 0x06), integer word 2 bit description 1 7 integer word n7 6 integer word n6 5 integer word n5 4 integer word n4 3 integer word n3 2 integer word n2 1 integer word n1 0 integer word n0 1 double-buffered. loaded on the write to register cr0. table 13. register cr7 (address 0x07), integer word 1 and muxout control bit description [7:4] muxout control 0000 = tristate 0001 = logic high 0010 = logic low 1101 = rclk/2 1110 = nclk/2 3 integer word n11 1 2 integer word n10 1 1 integer word n9 1 0 integer word n8 1 1 double-buffered. loaded on the write to register cr0.
adrf6750 rev. a | page 29 of 40 table 14. register cr9 (address 0x09), charge pump current setting bit description [7:4] charge pump current 1 0000 = 0.31 ma (default) 0001 = 0.63 ma 0010 = 0.94 ma 0011 = 1.25 ma 0100 = 1.57 ma 0101 = 1.88 ma 0110 = 2.19 ma 0111 = 2.50 ma 1000 = 2.81 ma 1001 = 3.13 ma 1010 = 3.44 ma 1011 = 3.75 ma 1100 = 4.06 ma 1101 = 4.38 ma 1110 = 4.69 ma 1111 = 5.00 ma 3 reserved 2 reserved 1 reserved 0 reserved 1 double-buffered. loaded on the write to register cr0. table 15. register cr10 (address 0x0a), reference frequency control bit description 7 reserved 1 6 r/2 divider enable 1 0 = bypass r/2 divider (default) 1 = enable r/2 divider 5 r-doubler enable 1 0 = disable doubler (default) 1 = enable doubler [4:0] 5-bit r-divider setting 1 00000 = divide by 32 (default) 00001 = divide by 1 00010 = divide by 2 11110 = divide by 30 11111 = divide by 31 1 double-buffered. loaded on the write to register cr0. table 16. register cr12 (address 0x0c), pll power-up bit description 7 reserved 6 reserved 5 reserved 4 reserved 3 reserved 2 power down pll 0 = power up pll (default) 1 = power down pll 1 reserved 0 reserved table 17. register cr14 (address 0x0e), txdis control bit description 7 reserved 6 reserved 5 txdis_attenuator 0 = attenuator always enabled (default) 1 = disable attenuator when txdis = 1 4 txdis_lobuf 0 = lobuf always enabled (default) 1 = disable lobuf when txdis = 1 3 txdis_quaddiv 0 = quaddiv always enabled (default) 1 = disable quaddiv when txdis = 1 2 reserved 1 txdis_lox2 0 = lox2 always enabled (default) 1 = disable lox2 when txdis = 1 0 txdis_rfmon 0 = rfmon always enabled (default) 1 = disable rfmon when txdis = 1 table 18. register cr23 (address 0x17), lock detector control bit description 7 reserved 6 reserved 5 reserved 4 lock detector enable 0 = lock detector disabled (default) 1 = lock detector enabled 3 lock detector up/down count 0 = 3072 up/down pulses 1 = 2048 up/down pulses 2 lock detector precision 0 = low, coarse (16 ns) 1 = high, fine (6 ns) 1 reserved 0 reserved
adrf6750 rev. a | page 30 of 40 table 19. register cr24 (address 0x18), autocalibration bit description 7 reserved 6 reserved 5 reserved 4 reserved 3 reserved 2 reserved 1 reserved 0 disable autocalibration 0 = enable autocalibration (default) 1 = disable autocalibration table 20. register cr27 (address 0x1b), lo monitor output and external vco control bit description 7 reserved 6 reserved 5 reserved 4 reserved 3 external vco control 0 = internal vco selected 1 = external vco selected 2 power up lo monitor output 0 = power down (default) 1 = power up [1:0] monitor output power into 50 00 = ?24 dbm (default) 01 = ?18 dbm 10 = ?12 dbm 11 = ?6 dbm table 21. register cr28 (address 0x1c), internal vco power-down bit description 7 reserved 6 reserved 5 internal vco power-down 0 = power up (default) 1 = power down 4 reserved 3 reserved 2 reserved 1 reserved 0 reserved table 22. register cr29 (address 0x1d), modulator bit description 7 reserved 6 reserved 5 reserved 4 reserved 3 reserved 2 reserved 1 reserved 0 power up modulator 0 = power down (default) 1 = power up table 23. register cr30 (address 0x1e), attenuator bit description 7 reserved 6 reserved [5:0] attenuator a5 to attenuator a0 000000 = 0 db 000001 = 1 db 000010 = 2 db 011111 = 31 db 110000 = 32 db 110001 = 33 db 111101 = 45 db 111110 = 46 db 111111 = 47 db table 24. register cr33 (address 0x21), revision code 1 bit description 7 revision code 6 revision code 5 revision code 4 revision code 3 revision code 2 revision code 1 revision code 0 revision code 1 read-only register.
adrf6750 rev. a | page 31 of 40 suggested power-up sequence initial register write sequence af ter applying power to the part, perform the initial register write sequence that follows. note that register cr33, register cr32, and register cr31 are read-only registers. also note that all writ- able registers should be written to on power-up. refer to the register map section for more details on all registers. 1. write register cr30: 0x00. set attenuator to 0 db gain. 2. write register cr29: 0x00. modulator is powered down. the modulator is powered down by default to ensure that no spurious signals can occur on the rf output when the pll is carrying out its first acquisition. the modulator should be powered up only when the pll is locked. 3. write register cr28: 0x01. power up the internal vco. write 0x21 if using an external vco. 4. write register cr27: 0x00. power down the lo monitor and select the internal vco. write 0x08 to select an external vco. 5. write register cr26: 0x00. reserved register. 6. write register cr25: 0x32. reserved register. 7. write register cr24: 0x18. enable autocalibration. 8. write register cr23: 0x70. enable lock detector and choose the recommended lock detect timing. 9. write register cr22: 0x00. reserved register. 10. write register cr21: 0x00. reserved register. 11. write register cr20: 0x00. reserved register. 12. write register cr19: 0x00. reserved register. 13. write register cr18: 0x00. reserved register. 14. write register cr17: 0x00. reserved register. 15. write register cr16: 0x00. reserved register. 16. write register cr15: 0x00. reserved register. 17. write register cr14: 0x1b. the attenuator is always enabled, even when txdis is asserted. 18. write register cr13: 0x18. reserved register. 19. write register cr12: 0x08. pll powered up. 20. write register cr11: 0x00. reserved register. 21. write register cr10: 0x21. the reference frequency doubler is enabled, and the 5-bit divider and r/2 divider are bypassed. 22. write register cr9: 0x70. with the recommended loop filter component values and r set = 4.7 k, as shown in figure 71 , the charge pump current is set to 2.5 ma for a loop bandwidth of 50 khz. 23. write register cr8: 0x00. reserved register. 24. write register cr7: 0x0x. set according to equation 1 in the theory of operation section. also sets the muxout pin to tristate. 25. write register cr6: 0xxx. set according to equation 1 in the theory of operation section. 26. write register cr5: 0x00. disable the 5-bit reference divider. 27. write register cr4: 0x01. reserved register. 28. write register cr3: 0x0x. set according to equation 1 in the theory of operation section. 29. write register cr2: 0xxx. set according to equation 1 in the theory of operation section. 30. write register cr1: 0xxx. set according to equation 1 in the theory of operation section. 31. write register cr0: 0xxx. set according to equation 1 in the theory of operation section. register cr0 must be the last register written for all the double-buffered bit writes to take effect. 32. monitor the ldet output or wait 170 s to ensure that the pll is locked. 33. write register cr29: 0x01. power up modulator. the write to register cr29 does not need to be followed by a write to register cr0 because this register is not double-buffered. examplechanging the lo frequency fol lowing is an example of how to change the lo frequency after the initialization sequence. using an example in which the pll is locked to 1200 mhz, the following conditions apply: ? f p fd = 20 mhz (assumed) ? divide ratio n = 60, so int = 60 decimal and frac = 0 the int registers contain the following values: register cr7 = 0x00 and register cr6 = 0x3c the frac registers contain the following values: register cr3 = 0x00, register cr2 = 0x00, register cr1 = 0x00, and register cr0 = 0x00 to change the lo frequency to 1230 mhz, the divide ratio n must be set to 61.5. therefore, int must be set to 61 decimal and frac must be set to 16777216 by writing to the following registers: 1. set the int registers as follows: reg ister cr7 = 0x00, register cr6 = 0x3d 2. set the frac registers as follows: register cr3 = 0x01, register cr2 = 0x00, register cr1 = 0x00, register cr0 = 0x00 note that register cr0 should be the last write in this sequence. writing to register cr0 causes all double-buffered registers to be updated, including the int and frac registers, and starts a new pll acquisition. if the cumulative frequency step is 100 khz or less, the user can turn off autocalibration. this process involves an additional write of 0x19 to register cr24, resulting in a smoother frequency step and shorter acquisition time.
adrf6750 rev. a | page 32 of 40 evaluation board general description thi s board is designed to allow the user to evaluate the performance of the adrf6750. it contains the following: ? i/ q modulator with integrated fractional-n pll and vco ? sp i and i 2 c interface connectors ? dc biasing and filter circuitry for the baseband inputs ? lo w-pass loop filter circuitry ? 10 mhz reference clock ? ci rcuitry to support differential signaling to the testlo inputs, including dc biasing circuitry ? ci rcuitry to monitor the lomon outputs ? sma connectors for power supplies and the rf output the evaluation board comes with associated software to allow easy programming of the adrf6750. hardware description for more information, refer to the circuit diagram in figure 71 . power supplies an external 5 v supply (dut +5 v) drives both an on-chip 3.3 v regulator and the quadrature modulator. the regulator feeds the vreg1 through vreg6 pins on the chip with 3.3 v. these pins power the pll circuitry. the external reference clock generator can be driven by a 3 v supply or by a 5 v supply. these supplies can be connected via an sma connector, vco +v. recommended decoup ling for supplies the external 5 v supply is decoupled initially by a 10 f capacitor and then further by a parallel combination of 100 nf and 10 pf capacitors that are placed as close to the dut as possible for good local decoupling. the regulator output should be decoupled by a parallel combination of 10 pf and 220 f capacitors. the 220 f capacitor decouples broadband noise, which leads to better phase noise and is recommended for best performance. case size c 220 f capacitors are used to minimize area. a parallel combi- nation of 100 nf and 10 pf capacitors should be placed on each vregx pin. again, these capacitors are placed as close to the pins as possible. the impedance of all these capacitors should be low and constant across a broad frequency range. surface-mount multilayered ceramic chip (mlcc) class ii capacitors provide very low esl and esr, which assist in decoupling supply noise effectively. they also provide good temperature stability and good aging characteristics. capacitance also changes vs. applied bias voltage. larger case sizes have less capacitance change vs. applied bias voltage and also lower esr but higher esl. the 0603 size capacitors provide a good compromise. x5r and x7r capacitors are examples of these types of capacitors and are recommended for decoupling. spi and i 2 c interface the spi interface connector is a 9-way, d-type connector that can be connected to the printer port of a pc. figure 70 shows the pc cable diagram that must be used with the provided software. there is also an option to use the i 2 c interface by using the i 2 c receptacle connector. this is a standard i 2 c connector. pull-up resistors are required on the signal lines. the cs pin can be used to set the slave address of the adrf6750. cs high sets the slave address to 0x60, and cs low sets the slave address to 0x40. 6 7 8 9 1 9-way female d-type 25-way male d-type to pc printer port gnd clk data le 2 3 4 5 21 22 23 24 25 8 9 10 11 12 4 5 6 7 1 2 3 16 17 18 19 20 14 15 13 pc 08201-022 figure 70. spi pc cable diagram
adrf6750 rev. a | page 33 of 40 baseband inputs the pair of i and q baseband inputs are served by sma inputs so that they can be driven directly from an external generator, which can also provide the dc bias required. an option is provided to supply this dc bias through connector j1, as well. there is also an option to filter the baseband inputs, although filtering may not be required, depending on the quality of the baseband source. loop filter a fourth-order loop filter is provided at the output of the charge pump and is required to adequately filter noise from the - modulator used in the n-divider. with the charge pump current set to a midscale value of 2.5 ma and using the on-chip vco, the loop bandwidth is approximately 60 khz, and the phase margin is 55. c0g capacitors are recommended for use in the loop filter because they have low dielectric absorption, which is required for fast and accurate settling time. the use of non-c0g capacitors may result in a long tail being introduced into the settling time transient. reference input the reference input can be supplied by a 10 mhz taitien clock generator or by an external clock through the use of connector j7. the frequency range of the reference input is from 10 mhz to 20 mhz; if the lower frequency clock is used, the on-chip reference frequency doubler should be used to set the pfd frequency to 20 mhz to optimize phase noise performance. testlo inputs these pins are differential test inputs that allow a variety of debug options. on this board, the capability is provided to drive these pins with an external 2 lo signal that is then applied to an anaren balun to provide a differential input signal. when driving the testlo pins, the pll can be bypassed, and the modulator can be driven directly by this external 2 lo signal. the se inputs also require a dc bias; the following two options are provided: ? a d c bias point of 3.3 v through a series inductor path. a resistor in parallel is provided to de-q any resonance. ? a dc bias point, which can be varied from 0 v to 3.3 v through a resistor divider network. note that these resistors should be large in value to ensure that the current drawn is small and that the resistors have little effect on the input resistance. if these pins are not used, ground them by inserting 0 resistors in r47 and r54. lomon outputs these pins are differential lo monitor outputs that provide a replica of the internal lo frequency at 1 lo. the single-ended power in a 50 load can be programmed to ?24 dbm, ?18 dbm, ?12 dbm, or ?6 dbm. these open-collector outputs must be terminated to 3.3 v. because both outputs must be terminated to 50 , options are provided to terminate to 3.3 v using on- board 50 resistors or by series inductors (or a ferrite bead), in which case the 50 termination is provided by the measuring instrument. if not used, these outputs should be tied to regout. ccompx pins the ccompx pins are internal compensation nodes that must be decoupled to ground with a 100 nf capacitor. muxout muxout is a test output that allows different internal nodes to be monitored. it is a cmos output stage that requires no termination. lock detect (ldet) lock detect is a cmos output that indicates the state of the pll. a high level indicates a locked condition, and a low level indicates a loss of lock condition. txdis this input disables the rf output. it can be driven from an exter- nal stimulus or simply connected high or low by jumper j18. rf output (rfout) rfout is the rf output of the adrf6750. rfout mod should be grounded in the user application.
adrf6750 rev. a | page 34 of 4 0 08201-072 user-defined value figure 71. applications circuit schematic
adrf6750 rev. a | page 35 of 40 pcb artwork component placement 08201-073 figure 72. evaluation board, top side component placement 08201-074 figure 73. evaluation board, bottom side component placement
adrf6750 rev. a | page 36 of 40 pcb layer information 08201-075 figure 74. evaluation bo ard, top sidelayer 1 08201-076 figure 75. evaluation board, bottom sidelayer 4
adrf6750 rev. a | page 37 of 40 08201-077 figure 76. evaluation board, groundlayer 2 08201-078 figure 77. evaluation board powerlayer 3
adrf6750 rev. a | page 38 of 40 bill of materials table 25. bill of materials qty reference designator description manufacturer part number 1 dut adrf6750 lfcsp, 56-lead 8 mm 8 mm analog devices adrf6750acpz 1 y2 vco, 10 mhz jauch o 10.0-vx3y-t1 1 spi connector, 9-pin, d-sub plug, sdex9pntd itw mcmurdo fec 150750 1 conn connector, i 2 c, semconn receptacle molex 15830064 2 c1, c21 capacitor, 10 f, 25 v, tantalum, taj-c avx fec 197518 13 c2, c4, c6, c8, c10, c12, c14, c16, c18, c19, c48, c53, c55 capacitor, 10 pf, 50 v, ceramic, c0g, 0402 murata fec 8819564 15 c3, c5, c7, c9, c11, c13, c15, c17, c22, c47, c49 to c52, c54 capacitor, 100 nf, 25 v, x7r, ceramic, 0603 avx fec 317287 1 c20 capacitor, 220 f, 6.3 v, tantalum, case size c avx fec 197087 4 c30 to c33 capacitor spacing, 0402 (do not install) 1 c26 capacitor, 1 nf, 50 v, xr7, ceramic, 0603 murata fec 722170 1 c24 capacitor, 47 nf, 50 v, xr7, ceramic, 1206 murata fec 1740542 2 c23, c25 capacitor, 680 pf, 50 v, npo, ceramic, 0603 murata fec 430997 4 c38, c39 capacitor, 1 nf, 50 v, c0g, ceramic, 0402 murata fec 8819556 4 c40, c44, c46, c57 capacitor, 100 pf, 50 v, c0g, ceramic, 0402 murata fec 8819572 12 j1 to j5, j7, j10 to j12, j14, j15, txdis sma end launch connector johnson/emerson 142-0701-851 3 j18, j20, j21 jumper, 3-pin + shunt harwin fec 148533 and fec 150411 4 l1, l2 inductor, 20 nh, 0402, lqw series murata lqw15an20n 4 l3, l4 inductor, 10 h, 0805, lqm series murata lqm21fn1n100m 4 r2 to r5 resistor spacing, 0603 (user-defined values) 5 r6 to r9, r36 resistor, 0 , 1/16 w, 1%, 0402 vishay draloric fec 1158241 2 r10, r11 resistor, 0402, spacing (do not install) 1 r13 resistor, 4.7 k, 1/10 w, 1%, 0603 bourns cr0603-fx-472 2 r14, r39 resistor, 1.2 k, 1/10 w, 5%, 0603 yageo fec 9233393 2 r12, r16 resistor, 270 , 1/16 w, 1%, 0603 multicomp fec 9330917 1 r15 resistor, 300 , 1/16 w, 1%, 0603 multicomp fec 93330968 2 r17, r18 resistor, 0603, spacing (do not install) 3 r35, r44, r45 resistor, 51 , 1/16 w, 5%, 0402 bourns cr0402-jw-510 4 r48 to r51 resistor, 330 , 1/10 w, 5%, 0805 bourns cr0805-jw-331 3 r59 to r61 resistor, 100 , 1/10 w, 5%, 0805 bourns cr0805-jw-101
adrf6750 rev. a | page 39 of 40 outline dimensions compliant to jedec standards mo-220-vlld-2 041807-b pin 1 indicator top view 7.75 bsc sq 8.00 bsc sq 1 56 14 15 43 42 28 29 4.95 4.80 sq 4.65 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 0.20 ref 12 max 0.80 max 0.65 typ 1.00 0.85 0.80 6.50 ref seating plane 0.60 max 0.60 max pin 1 indicator coplanarity 0.08 0.05 max 0.02 nom 0.30 min exposed pad (bottom view) for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 78. 56-lead lead frame chip scale package [lfcsp_vq] 8 mm 8 mm body, very thin quad (cp-56-3) dimensions shown in millimeters ordering guide model 1 temperature range package description package option adrf6750acpz-r7 ?40c to +85c 56-lead lead frame chip scale package [lfcsp_vq], 7" tape and reel cp-56-3 ADRF6750-EVALZ evaluation board 1 z = rohs compliant part.
adrf6750 rev. a | page 40 of 40 notes i 2 c refers to a communications protocol originally develo ped by philips semiconductor s (now nxp semiconductors). ?2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d08201-0-4 /10(0)

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